Pulse regenerating repeater

ABSTRACT

A PULSE REGENERATING REPEATER TO BE INSTALLED IN CASCADE IN A TRANSMISSION LINE TO REGENERATE ATTENUATED PULSES WHEREIN THE REPEATER CONSISTS OF A SERIES CONNECTION OF A WAVE REGENERATING CIRCUIT, A DELAY LINE AND A REFLECTING CIRCUIT RESPECTIVELY. AN ATTENUATED AND PHASE JITTERED INOPUT PULSE IS REGENERATED BY THE WAVE REGENERATING CIRCUIT AND THEN PROPAGATED ON THE DELAY LINE AND THE PORTION OF THE REGENERATED PULSE WHICH IS ABOVE A PRESELECTED CRITICAL VALUE OF THE REFLECTING CIRCUIT IS PASSED THERETHROUGH FOR TRANSMISSION AND THE REMAINING PORTION BELOW THIS CRITICAL VALUE IS REFLECTED TO FORM A TIMING PULSE WHICH IS SHUTTLED BACK AND FORTH ON THE DELAY LINE. THE SIMULTANEOUS PRESENCE OF AN INPUT PULSE AND A TIMING PULSE AT THE WAVE REGENERATING CIRCUIT TRIGGERS A NEGATIVE RESISTANCE DEVICE THEREIN, WHEREBY THE PULSE IS REGENERATED SUCH THAT THE RETIMING OF THE REGENERATED PULSE IS CONTROLLED AT THE ORIGINAL FUNDAMENTAL FREQUENCY BY THE TIMING PULSE.

Feb. 2,1971

TSUNEO NAKAHARA ET AL PULSE REGENERATING REPEATER lO Sheets-Sheet 1 Filed Aug` 24, 1966 l@ A Awww BY Yu. #0.5mm

THe/@Arroene'vs NSG \ Feb. z, 1911 10 Sheets-Sheet 2 Filed Aug. 24, 1966 5 e... 5J Y mui ww MA U o f Wmmm 14mm. r Neva/ wm w Wsw @m BMV N. m M a Www TsuNEo NAKAHARA ET AL 3,560,857

Feb. 2, 1971 PULSE HEGENERATING REPEATER 1o sheets-sheet 4.

Filed Aug. 24. 1966 55 u# #Y .mm mmwnre Nl 0 EMM?, 1H CA .vr` .mw/sm J umn-m TY m Q ,Tu s+ Feb. 2, 1971 TSUNEO NAKAHARA ETAL 3,560,857

PULSE REGENERATING REPEA'I'ER lO Sheets-Sheet 7 Filed Aug. 24. 1966 s s EN w .f w mmwA M e mmmz a m VA l A g I wus A A P L Qvwc e ...w/d n Wsw a m v l M vm M Qwxuv a QWWNS M C nvm@ l-l Q ..w\ 3 .4. mab @amv No i Q s Q\\ Qwv v aww .u nos lf im m Riv E? s QQ i QN um Feb-'2,1971 TsuNEo NAKAHARA ETAL PULSE REGENERATING REPEATER l0 SheetsfSheet 8 Filed Aug. 24, 1966 QNG w inw.

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,s .2 u OA U H 1H-.A mA/xw VK m l HMA wMumC .ww/f WSWS BmYn s TsuNEoNAKAHARA ETAI.' 3,560,857

Feb. 2, 1971 PULSE REGENERATING REPEATER Filed Aug. 24, 196e l0 Sheets-Sheet 9 Mw. M

1 vENToR 73 aun A/KA M454, BY YA sua y.5M/Ml zu YuJ/ KosAKA @Aeon-fees Camz-#frs 7715/2 4 Trams/v5 United States Patent O U.S. Cl. 325--38 12 Claims ABSTRACT F THE DISCLOSURE A pulse regenerating repeater to be installed in cascade in a transmission line to regenerate attenuated pulses wherein the repeater consists of a series connection of a wave regenerating circuit, a delay line and a reflecting circuit respectively. An attenuated and phase jittered input pulse is regenerated by the wave regenerating circuit and then propagated on the delay line and the portion of the regenerated pulse which is above a preselected critical value of the reflecting circuit is passed therethrough for transmission and the remaining portion below this critical value is reflected to form a timing pulse which is shuttled back and forth on the delay line. The simultaneous presence of an input pulse and a timing pulse at the wave regenerating circuit triggers a negative resistance device therein, whereby the pulse is regenerated such that the retiming of the regenerated pulse is controlled at the original fundamental frequency by the timing pulse.

The present invention relates to pulse regenerating repeaters for a pulse transmission system. More particularly, it relates to a pulse regenerating repeater wherein a wave is regenerated and transmitted, the series of pulses which have deteriorated as propagated along the transmission line being regenerated to correct values and positioned on the time axis to have correct time intervals `between pulses.

If a pulse is transmitted by a transmission line, the amplitude of the pulse attenuates owing to the transmission loss. It is, consequently, necessary to regenerate the wave by interposing repeaters at suitable intervals. With pulse transmission, on the other hand, not only the amplitude of the pulse is important, but the frequency of the pulse is also important. If the interval between pulses arriving at the receiving terminal is in disorder, it is impossible to obtain correct information even if the amplitude of the pulse arriving there is great enough. The controlling of the time of wave regeneration at each repeater on the basis of some time standard for the purpose of keeping the pulse interval at a constant value is called retiming.

The object of the present invention is to obtain a pulse regenerating transmission line which has a retiming function based on a new principle. The method of retiming which has hitherto been employed commonly is one wherein the fundamental frequency of the pulse train is extracted by a resonating oscillation system based on the combination tank circuit of inductance and capacitance and the time for wave regeneration is thereby determined. The method of the present invention, on the other hand, effects retiming by making use of a forced oscillation system based on the shuttling phenomenon on a transmission line of a xed length instead of the resonating phenomenon of the LC circuit. That is to say, a part of the energy of the output pulse made by the wave regenerating circuit ins caused to continue shuttling on a transmission line of a Xed length the ends of which are ice terminated under suitable conditions, and the fact that the shuttling takes place at a fixed interval because the speed of the pulse proceeding along this transmission line is constant, is utilized for effecting the retiming. It has a characteristic feature in that a retiming of greater stability and higher quality can be effected by a simple structure which does not necessitate an LC resonating circuit.

It is possible to use a part of the transmission line itself as the said transmission line of a fixed length .for retiming` That is to say, it is possible to construct a pulse regenerating transmission line having the retiming function based on the principle of the present invention by placing a wave regenerating circuit and non-linear active reflecting circuit with a xed section of the transmission line in-between. This wave regenerating circuit and nonlinear active reflecting circuit can both be simply realized by the use of a Z-terminal negative resistance device. Thus it is another object of the present invention to obtain a pulse regenerating transmission line having retiming function, with these two circuits insalled in a transmission line with a fixed section of the transmission line interposed between them.

The fact that the present invention attains the aforementioned objects will be made clear if its embodiments are studied with reference to the drawings as explained below.

Other objects and advantages appear hereinafter in the following description and claims,

The accompanying drawings show for the purpose of exemplication without limiting the invention or claims thereto, certain practical embodiments illustrating the principles of this invention wherein 1:

FIG. 1 is a schematic diagram showing the basic principle of the present invention. FIG. 2 is a schematic diagram showing an embodiment of the invention. FIGS. 3a

and 3b are schematic diagrams showing the construction of a composite transistor circuit. FIG. 4 is a graph showing the voltage-current (V-I) characteristic of the circuit of FIG. 3. FIGS. 5a and 5b are schematic diagrams showing the construction of a composite transistor circuit. FIG. 6i is a graph showing the V-I characteristic ofthe circuit of FIG. 5. FIG. 7 is a graphical plot showing the reflection characteristic and transmission characteristic of Block C of FIG. 2. FIG. 8 is a graphical illustration showing the operation of the embodiment of FIG. 2. FIG. 9 is a schematic diagram showing another embodiment of the present invention. FIGS. 10a and 10b are schematic diagrams showing the construction of a composite transistor circuit. FIG. 11 is a graphical plot showing the V-I characteristic of the circuit of FIG. 10. FIG. 12 is a graphical plot showing the reflection characteristic and transmission characteristic of Block C of FIG. 9. FIG. 13 is a graphical illustration showing the operation of the embodiment of FIG. 9. FIG. 14 is a schematic diagram showing another embodiment of the present invention. FIG. 15 is a graphical illustration showing the operation of the embodiment of FIG. 14. FIG. 16 is a schematic diagram showing another embodiment of the present invention. FIG. 17 is a graphical illustration showing the operation of the embodiment of FIG. 16. FIGS. 18, 19, 20 and 21 are schematic diagrams, each showing different embodiments of the present invention. FIGS. 22a and 2211 are schematic diagrams showing the construction of a composite transistor circuit. FIG. 23 is a graphical plot showing the V-I characteristic 5f the circuit of FIG. 22.

FIG. 1 is a diagram showing the basic principle of the present invention. The structure from terminals 1-1 to terminals 4 4 constitutes one repeating block.

One repeating `block of this invention consists of the three blocks A: wave regenerating circuit, B: pulse delay line and C: nonlinear active reliecting circuit. A is a pulse circuit having a threshold level and makes wave regeneration. B is a delay line of a fixed length and gives a fixed delay to the pulse. C is a non-linear amplifying reecting circuit. It has such a reection characteristic that if the amplitude of the incident pulse coming from 3-3 is smaller than a certain value, it reflects the pulse with amplication, while the amplitude of the reflected pulse for the incident pulse having a larger amplitude than a certain value is saturated at the xed value.

Since the amplitude of the regenerated pulse of the wave regenerating circuit A is made sufliciently greater than the critical value at which the reflection characteristic of the non-linear active reflecting circuit C enters the region of saturation, only a part of its energy is reflected by the reflecting circuit C, a greater part of it passing through the reflecting circuit C without being reflected and being sent out to the next stage to become output pulse. A part of the energy of the regenerated pulse made by the wave regenerating circuit A becomes a small amplitude pulse which returns to the wave regenerating circuit A. If the reection at terminals 2-2 of this small amplitude pulse due to the selected terminal impedance of circuit A is made a reflection with small loss, the said small amplitude pulse can be caused to shuttle continuously on the pulse delay line B limited between the wave regenerating circuit A and the reilecting circuit C by having the reflection loss at the wave regenerating circuit A and the transmission loss at the delay line B almost compensated by the reflection gain at the reecting circuit C. As this shuttling phenomenon is a cyclic phenomenon having a fixed cycle proportional to the pulse propagation time on the delay line B, the retimed regeneration can be made by controlling the point of time of wave regeneration by the wave regenerating circuit A by means of the aforementioned small amplitude pulse applied from terminals 2-2. Naturally it is necessary that the Wave regenerating circuit A should be such a pulse circuit that is triggered by the energy which is the sum of the input pulse applied to terminals 1-1 and the small amplitude pulse for timing applied vfrom terminals 2-2'.

FIG. 2 shows an embodiment of the present invention. In FIG. 2, pulse source block (S) comprises pulse generator 8 with impedance 9, coupling condenser C110 and constant current power source 7 to supply each repeating block, transmission blocks L1 and L2 comprise transmission lines and repeating blocks and load block F comprises load 101, coupling condenser C120 and constant current power source 7.

The part from terminals 1-1' to terminals 2 2 corresponds to the block A of FIG. 1, the line B to the block B and the part from terminals 3-3' to terminals 4-4 to the block C.

The pulse delay line B may either be one of the same type as other transmission lines or be some other special delay line. For convenience in explaining, however, the characteristic impedance of all the lines will be considered to be Z0.

From the pulse generator 8 of impedance 9, pulses are transmitted to the load 10 through the whole pulse transmission line, and each repeater circuit inserted in the transmission line is supplied with electric power by Zener diode biased by D.C. current supplied to the line by constant current sources 7, 7 which are connected to the terminal ends or source and load ends of the transmission line.

In FIG. 2, condensers C101-C100 are all coupling condensers or bypass condensers, and show impedance small enough for signals. Inductances L100-L105 are all choke coils and show impedance large enough for signals.

The block A comprises an impedance converter using transistor T100 of a common-base configuration and a bistable biased composite transistor circuit NW showing N- type (voltage regulated type) negative resistance.

Regulated by the resistances R and R101, the impedance converter has an input impedance equal to the irnpedance Z'o of the line and an output impedance suiciently greater enough than Zo. The composite transistor circuit NW is a circuit as shown in FIG. 3(a), represented by a symbol given in FIG. 3(b). In FIG. 3(a), t1, t1' and P1 are terminals, T15 and T10 are transistors, R11, R12 and R13 are resistors, E10 is a constant voltage power source. V shows a voltage applied between terminals l1 and t1', and is defined to take positive value wherein a potential at terminal t1 is higher than that at terminal l1. I shows a current which flows into terminal l1 and ows out from terminal t1. The voltage-current characteristic of this circuit between the terminals t1-t1' shows an N- type negative resistance as shown in FIG. 4.

There are two positive resistance regions which are separated by a negative resistance region in the voltagecurrent (V-I) characteristic curve shown in FIG. 4. The one at the smaller voltage side of the negative resistance region is called rst positive resistance region, the other is called second positive resistance region.

The various values defining the V-I characteristic curve are as follows:

VP1: a voltage of the transition point between the negative resistance region and the rst positive resistance region VV1: a voltage of the transition point between the negative resistance region and the second positive resistance region Ra1-1: a gradient in conductance of the V-I curve in the first positive resistance region R01-1: a gradient in conductance of the V-I curve in the negative resistance region R71-1: a gradient in conductance of the V-I curve in the second positive resistance region These values are given in the following formulae using circuit constants shown in FIG. 3(a):

Ell)

where, Vd15 and Vd11, are the emitter diffusion potentials of transistors T15 and T10 respectively. As regards the composite transistor circuit used in the embodiments of this invention, reference to Belgian Patent 551,746, for example, is suggested.

The composite transistor NW is biased at Point A1 in FIG. 4 by Zener diode D100 and resistances R102, R102, and choke coil L103. The straight line r11-a1 is a D-C load line. The straight line b1-b1 is an A-C load line. As the output impedance of the impedance converter is great enough, this gradient is about Z0-1.

Since the terminating impedance at terminals 2-2', which is comprised of the parallel connection of the output impedance of the impedance converter and the impedance of the Nw-bistable circuit in the area of the operating point A1 as shown in FIG. 4, is very much larger than the characteristic impedance Zo of the line B, the small amplitude incident pulse (namely, the timing pulse) applied to the terminals 2-2' is reected there with the same polarity and with a low reflection loss.

Since RaflzO, NW gives a high impedance against small amplitude pulses not exceeding threshold level VP1-VO1 in the proximity of Point A1. If a positive input exceeding the threshold level is applied between t1, t1',

Nw is triggered and, via Points B1 and C1, is switched to a high potential condition D1 and generates a positive large amplitude voltage step. Point D1 not being a directcurrent-wise stable point, the operating point of circuit NW shifts gradually from D1 to E1 in accordance with a very large time constant determined mainly by L103, but it may be considered to be an approximate stable point where the time is so short as compared to the in` terval of signal pulse repetition. If a negative input so large that the operating point of NW exceeds Point E1 is applied to Nw located at Point D1, Nw is again triggered and, via Points E1, F1, is switched to Point A1 and generates a negative large amplitude voltage step. That is to say, NW in FIG. 2 effects a bistable action.

The block C is a circuit wherein a composite transistor circuit S1 showing an S-type (current regulated type) negative resistance is stably biased in its negative resistance region and connected in parallel to the line. The composite transistor circuit Sr is a circuit as shown in FIG. 5 (a) and is represented by a symbol given in FIG. 5 (b). In FIG. 5 (a), t1, t4 and P1 are terminals, T45 and T40 are transistors, R41, R42, R43 are resistors, E40 is a constant voltage power source. V shows a -voltage applied between terminals t1 and t4 and is defined to take positive `value wherein a potential at t4 is higher than that at terminal t4. I shows a current which llows into terminal t4 and flows out from i4. The voltage-current characteristic of this circuit between terminals t4-tr1 is of an S-type negative resistance as shown in FIG. 6. In FIG. 6 there are two positive resistance regions which are separated by a negative resistance region. The one at the smaller current side of the negative resistance region is called the first positive resistance region, the other is called the second positive resistance region.

The various characteristic values of the V-I characteristic curve are as follows:

-11142 a current of the transition point between the negative resistance region and the rst positive resistance region -Vv4z a voltage of the transition point between the negative resistance region and the second positive resistance region RM1-1: `a gradient in conductance of the V-I curve in the first positive resistance region RM-1: a gradient in conductance of the V-I curve in the negative resistance region R751: a gradient in conductance of the V-I cur-ve in the second positive resistance region These values are given in the following formula using circuit constants shown in FIG. 5 (a) Where, Vd45 is the emitter diffusion potential of tran SSOI T45.

The composite transistor circuit SJF is biased at Point A by Zener diode D101; resistances R104, R105; and coil L105.

The straight line r4-a4' is a D-C load line.

The straight line hr1-b4 is an A-C load line, and its gradient is Z0 The reflection characteristic and transmission characteristic at terminals 3-3 are shown in FIG. 7. The reflection coeflicient K14 and transmission coefllcient KM at 6 terminals 3-3 for such a small amplitude input are such that the operating point of the composite transistor circuit Sr does not get out of the negative resistance region of its V-I characteristic and are given by the following:

Z0 As R114 is selected so that Z0/2 R4, K14 -1, and the small amplitude pulse is reflected with amplification changing its polarity.

The value of K14 is so set that self-oscillation between the waive regenerating circuit A and reflecting circuit C 1will not take place though the rellection gain of the refleeting circuit Sr almost compensates the transmission loss at the delay line B and the reflection loss at terminals 2 2. Usually, as both losses at the delay line and the terminals 2-2 are made small enough, the value of K14 is equal to approximately ml and consequently the value of Kp, is approximately 0. That is to say, the small amplitude pulse shuttling in the delay line B generally seldom gets transmitted through the Sr reflection circuit.

Since ILA-1:0 as shown in FIG. 6, the reflected pulse by the reflecting circuit Sr for an input pulse of or more gets a constant value of zu Iti not depending on the amplitude of the input wave. This is so set that it is adequately smaller than the amplitude value of the regenerated output pulse by the N10-bistable circuit, so that a greater part of the energy of the regenerated output pulse of the NW`bistable circuit is transmitted through the Sr-reilecting circuit and only a part of the energy determined -by the staurated reflection level of the Sr-reflecting circuit is reilected by the Sr-rellecting circuit.

The regenerating repeater system consisting of the above-described circuits operates as follows:

Let 1- represent one way propagation time of the delay line B, and this system regenerates and transmits a pulse train whose fundamental interval T is equal to 4T.

Now we will explain the case `where the threshold level of the NW-bistable circuit is so set that the NW-bistable circuit cannot be triggered by the input pulse by itself, but is triggered only when the input pulse and the small amplitude pulse shuttling on the delay line B are applied simultaneously.

An input pulse arriving at terminals l-l at a time t=t0 when there exists no pulse on the delay line B does not trigger the NW-bistable circuit. but is transmitted to the delay line B, is reilected with amplification changing its polarity at terminals 3-3' because the critical value of the reflecting circuit C, having the reflection characteristics as shown in FIG. 7, is so set that it is larger than the amplitude of the input pulse. This reflected pulse is applied in negative polarity to the N10-bistable circuit from terminals 2 2 at time t=t0l2r. Since the resultant impedance of the circuit NW and the impedance converter is large enough relative to the small amplitude pulse, this negative pulse is reflected in the same polarity, reaches the Sr-reilecting circuit, is again reflected with amplication changing its polarity at terminals 3-3, and is applied to the NW-bistable circuit as a pulse of positive polarity at time t=t0l4n As already mentioned, the reflection gain of the Sy rellecting circuit is restricted to such a value that no Self 7 oscillation between the wave regenerating circuit A and the reflecting circuit takes place, so that the amplitude of the pulse applied to the NW-bistable circuit at time t=t11i4T is slightly smaller than that at t=t0. Since the fundamental interval of the input pulse is a 4T, there is possibility of the next input pulse existing at time t=t0i4n If the next input pulse is present, it is added to the said 2round trip preceding pulse. In case the next input pulse does not exist, no addition is made. The said procedure is repeated in either case. Where the average arrival frequency of the input pulse is given, it is always possible to make a setting such that the amplitude of the shuttling pulse on the delay line B increases by adjusting the reflection gain of the Sr-reflecting circuit. For, if the reflection gain of the Sr-reflecting circuit is made larger until just before the system oscillates, the shuttling pulse can be caused to increase in amplitude, no matter how small the arrival frequency is. In actuality, an arrival frequency that need not increase the gain so much as to have the system nearly begin oscillating can be expected. When the amplitude of the pulse shuttling on the delay line B has become so large that the sum of it and the input pulse can trigger the NW-bistable circuit, let us call this particular shuttling pulse the timing pulse.

When the ratio of the crest value of the input to the value of the threshold level of the nonlinear negative resistance of the wave regenerating circuit is too small to trigger the nonlinear negative resistance, the input pulSe passes through the wave regenerating circuit and is reflected by the reflecting circuit to shuttle between the Iwave regenerating circuit and the reflecting circuit to become a timing pulse.

The succeeding several input pulses are not regenerated and are consumed to build up the timing pulse until the resultant value of an input pulse and timing pulse exceeds the threshold value of the wave regenerating circuit. Consequently, when the ratio of the value of input signal to the threshold value is small, it is a general practice to send several pilot pulses for the growing of the timing pulse at the beginning of the communication.

If an input pulse arrives after the growth of the timing pulse, the Nw-bistable circuit is triggered and switched from the low potential to the high potential state D1 shown in the characteristic curve of FIG. 4, as a positive large amplitude voltage step being generated. This large amplitude positive voltage step is sent out to the line B and to the reflecting circuit C. The reflecting circuit C has a characteristic curve having a critical value as shown in FIG. 6 so that the large positive voltage step is divided in two parts, a smaller portion being reflected by the rcflecting circuit C with its polarity changed and the remaining larger portion being passed through the reflecting circuit C. When the time of 2T passes from the first switching, the NW-bistable circuit is again triggered and switched by the said reflection small amplitude voltage step of negative polarity from the high potential state D1 to low potential state A1 and a negative large amplitude voltage step, having an amplitude equivalent to one of the large positive voltage steps, is generated by the NW bistable circuit. The preceding large positive step and the large negative voltage step following behind by 2T compose a positive pulse having a width 2T and a large amplitude which is sent out from terminals 4-4 via the delay line and reflecting circuit (the large negati-ve pulse increases the fall length of the trailing edge of the positive pulse to provide in effect a large positive pulse.) A part of the energy is reflected by the Sr-rellecting circuit with its polarity changed. A new timing pulse is produced by this small amplitude reflection step of positive polarity and continues shuttling between the wave regenerating circuit A and the reflecting circuit C gradually attenuating itS amplitude until the arrival of the next input pulse.

Consequentially, in the regenerating repeater system of FIG. 2, the input pulse train is wave-regenerated and re- 8 timed into the output pulse train having width 2T and fundamental interval 4r.

FIG. 8 shows an outline of the operation of the circuit. In that Figure, I is the input wave form observed at terminals 1-1 of FIG. 2, II isthe voltage wave form of NW observed at the 2 terminals t1-t1 of the composite transistor circuit NW of FIG. 2, and III is the output wave form observed at terminals 4-4.

l`he figure shows a case where a pulse train of pattern 10011 'is sent out from the pulse source 8, transmitted or. the transmission line L1 and applied to the input terminals 1-1 as an input pulse train, P1, P1 and P1 attenuated and having phase jitters, while the small amplitude timing pulses II having the duration 2T are formed already in the delay line B.

When the input pulse P1 and a timing pulse are applied to the Nw-bistable circuit at a time t=t0 simultaneously, the resultant wave form formed by these two pulses exceeds the threshold level of the NW-bistable circuit at the time t=t0 because the timing pulse has a steep leading edge, and thus triggers the Nw-bistable circuit and generates a large amplitude positive voltage step.

This large amplitude positive voltage step is transmitted on the line B and arrives at terminals 3-3 of the reflecting circuit C at a time tzto-l-T. When the large amplitude positive step arrives at the reflecting circuit C which has a characteristic curve having a critical value as shown in FIG. 6, a large part of the voltage step exceeding the critical value and passes through the reflecting circuit but the remainder is reflected towards the 'NW-bistable circuit with the opposite polarity and triggers again the NW-bistable circuit and generates a negative voltage step as large as the aforementioned positive voltage step at a time t=t0i27l The large negative voltage step discontinues the large positive pulse at t=t0+21 to give a resultant positive pulse of duration 21- and of twice the magnitude of either large pulse alone as the fall of the positive pulse is doubled due to the addition of the negative rise. A small portion of this pulse is, of course, reflected by circuit C. This large portion not reflected is the regeneration pulse of input pulse P1. Input pulses P1 and P1" are regenerated in the same manner.

However, if a positive timing pulse is only applied to the Nw-bistable circuit and an input pulse is not present at the time t=t0l41, this timing pulse is reflected at terminals 2-2 with the same polarity and low loss because the terminating impedance of terminals 2-2 is very large for a small amplitude pulse, and propagates on the delay line B, arrives at the reflecting circuit C and is reflected there with amplification toward terminals 2-2 with opposite polarity and suilicient amplification to compensate the reflection loss of the wave regenerating circuit and the transmission loss of the delay line B. The timing pulse arriving at terminal 2-2 is reflected in the same manner mentioned before, propagates again on the delay line B, arrives at the reflection circuit C, is reflected at the reflecting circuit C With opposite polarity and propagates on the delay line B towards terminals 2-2 and again arrives at terminals 2-2 at the time t=t0l8r- In such a way, a timing pulse having the duration of 21- shuttles between the wave regenerating circuit and the reflecting circuit C with the fundamental period of 41- and the attenuation of the amplitude of the timing pulse is compensated by the amplification of the reflecting circuit C. The timing pulse continues shuttling until a following input pulse arrives.

The above explanation of the operation Ihas been made concerning a case where the input pulse by itself cannot trigger the NW-bistable circuit.

However, when we design to make the ratio of the value of the input pulse applied at terminals 1-1 to the threshold value of the -NW-bistable circuit large, input pulses are immediately regenerated, but the accuracy of the retiming of the regenerated pulses are poor until the timing pulses are formed steadily. If the leading edge of the input pulse is extremely steep, the N13-bistable circuit is triggered by the contribution of the input pulse alone so that the timing pulse is not effective for the retiming of the regeneration pulse.

Since the Wave form of the input pulse attenuated on the transmission line has generally a slanted rise at the leading part of the input pulse wave form and the timing pulse has a step rise at its leading part, the retiming moment is determined by the leading part of the timing pulse.

As stated above, the present invention makes it possible to effect more stable retiming in a simple manner, using the pulse propagation time on the line of a fixed length as a basis for retiming without using the ordinary LC resonating circuit.

FIG. 9 shows another embodiment. A composite transistor circuit NW is operated as a monostable circuit, and an N-type negative resistance circuit Nr connected in series to the line is used as the nonlinear active reflecting circuit C201-C233 are coupling condensers or bypass condensers and have impedance small enough for signals. L203 is a coil for the purpose of the monostable operation of the composite transistor circuit NW and the value of its inductance is set so as to make the Width of the output pulse by monostable operation have a prescribed value. With the exception of the coil L303, the wave regenerating circuit A is quite similar to that of the embodiment shown in FIG. 2. In FIG. 4, the D-C load line and A-C load line of the circuit NW are shown by straight line a1-a1 and straight line L11-b1 respectively.

`In the NW-monostable circuit, the value of inductance of the coil L303 is not made so great as that of L103 in the NW-bistable circuit, but is so set that the transition from high potential state D1 to bottom point E1 quickly takes place in a time shorter than the fundamental repetition interval of the signal pulse train.

That is to say, the composite transistor circuit of FIG. 9 performs such a monostable operation that it is triggered by one positive input pulse and is switched to a high potential state and, after the elapse of a fixed length of time W determined by coil 14203, jumps itself to a low potential state. Block C is a composite transistor circuit Nr with an N-type negative resistance being connected in series to the line and stably biased in its negative resistance region. The composite transistor circuit Nr is a circuit as shown in FIG. 10(a) and is represented by a symbol as shown in FIG. 10(1)). In FIG. 10(a), t3, t3 and P3 are terminals, T35 and T36 are transistors, R31, R33 and R33 are resistors, E33 is a constant voltage power source, D37 is a diode. V shows a voltage applied between terminals t3 and t3', and is defined to take positive value wherein a potential at t3 is higher than that at terminal t3. I shows a current which flows into terminal t3 and flows out from terminal t3. The voltage-current characteristic of this circuit between terminals t3t3 shows such a negative resistance of an N-type as shown in FIG. 1l. In FIG. 11, there are two positive resistance regions which are separated by a negative resistance region. The one at the smaller voltage side of the negative resistance region is called first positive resistance region, the other is called second positive resistance region.

The various characteristic values of the V-I characteristic curve are as follows:

-VP3: a voltage of the transition point between the negative resistance region and the first positive resistance region -Vv3z a voltage of the turning point in the negative resistance region V113: a voltage of the transition point between the negative resistance region and the second positive resistance region IU R334: a gradient in conductance of the V-I curve in the first positive resistance region R33 1: a gradient in conductance of the V-I curve in the negative resistance region R.,3"1: a gradient in conductance of the V-I curve in the second positive resistance region These values are given in the following formulae using circuit constants shown in FIG. 10(a):

vez (Vds. +f- Vd...)

Where, V335 and V333 are the emitter diffusion potentials of transistors T35 and T33 respectively, V337 is the diffusion potential of diode D37, and V137 is the forward resistance of diode D37. The composite transistor circuit Nr is biased at Point A3 with constant voltage diode D301; resistances R205, R204; COllS 1.1205, 172206, 14207. The Straight line Z3-a3, is the D-C load line. The straight line b3-b3 is the A-C load line, and its gradient is The reflection characteristic and transmission characteristic at terminals 3-3 are shown .in FIG. 12. The graph of FIG. 12 is a graph obtained by approximation on the assumption that in FIG. 11 negative resistance R33 is shown also in the voltage range -VV3/ V VV3.

Reflection coecient K13 and transmission coe'icient Kw at terminals 3-3 for such a small amplitude input that the operating point of the composite transistor N1. may not get out of the negative resistance region of its V-I characteristic may be given by the following formulae:

Since R33 is so selected that 2Z3 R33, 1 Kr3, the small amplitude pulse is reffected with amplification without changing its polarity by the Nr-reilecting circuit.

The value of Kr3 is so set that no self-excited oscillation takes place between the wave regenerating circuit A and the reflecting circuit C, although the transmission loss at the delay line B and the reflection loss at terminals 2-2 are almost all compensated by the reflection gain of the Nr-reflecting circuit. As losses at the delay line B and terminals 2-2 can usually be made sufficiently small, the value of K13 is equal to approximately +1 and consequently the value of K13 is approximately 0. That is to say, usually the small amplitude pulse shuttling on the delay line B is scarcely transmitted through the Nr reflecting circuit. As shown in FIG. 1l,

far

l l Consequently, as shown in FIG. 12, the reflection wave of the Nr-reflecting circuit has a constant value of VoaJrVw,

as against any input wave not less than (21E-Rigs) X (Vos-i-Vva) independent of the amplitude of the input wave.

This critical value is so set that it is adequately smaller than the value of amplitude of regenerated output wave of the NW-monostable circuit and a greater part of the energy of the re generated output pulse of the Nw-monostable circuit is' transmitted through the Nr-reflecting circuit, only a part of the energy determined by the saturated reflection level of the Nr-reflecting circuit being reflected by the Nr-refleeting circuit.

The pulse regenerating system of FIG. 9 which comprises the above-described circuits operates as follows: In this case, twice the time of the one-way propagation on the delay line B is made equal to the fundamental repetition interval of the input pulse train. In the system of FIG. 9, both terminals of the delay line B are so terminated that the small amplitude pulse is reflected without changing its polarity, so that the one cycle of the shuttling on the delay line B is equal to 2T. In case a pulse train having a fundamental interval of 2T and an amplitude smaller than the threshold level of the NW-monostable circuit arrives, it is always possible to adjust the reflection gain of the N,.-reflecting circuit and make setting such that the timing pulse is produced on the delay line B without allowing the system to oscillate. If an input pulse arrives after the production of a timing pulse, the NW- monostable circuit is triggered and generates a regenerated pulse having a width W. In this situation, the output pulse width is determined by the Nw-monostable circuit alone, having nothing to do with T. A part of the energy of the regenerated pulse generated by the Nw-monostable circuit is reflected by the Nr-reflecting circuit and becomes a new timing pulse, and continues shuttling again between the wave regenerating circuit A and the reflecting circuit C, with its amplitude gradually diminishing, until the next input pulse arrives.

FIG. 13 shows an outline of the operation of the pulse regenerating system of FIG. 9. I in FIG. 13 shows the input wave form observed at terminals tl-tl of the NW- monostable circuit, II is the wave form observed at terminals 2-2 and III is the output wave form observed at terminals 4-4.

FIG. 13 shows a case where the timing pulse has been permitted to grow in the pulse regenerating system.

When the input pulse P1 and any timing pulse are applied to the Nw-monostable circuit at a time t-to simultaneously, the resultant wave form formed by the two pulses exceeds the threshold level of the Nw-monostable circuit at the time t=t and triggers the Nw-monostable circuit, because the timing pulse has a steep edge at its leading part when the time is tzto, and generates a large amplitude positive voltage pulse having a width W as a regeneration pulse of input pulse P1.

This large voltage step is transmitted on the line B and applied at terminals t3-t3 of the Nr-reflecting circuit having a V-I characteristic curve as shown in FIG. l1, at a time t=z0-]-r. When the large amplitude positive pulse arrives at the N,.reflecting circuit, a large part of the regenerated pulse exceeding the critical value of the refleeting circuit passes over or through this circuit, and another part of the regenerated pulse is reflected towards the Nw-monostable circuit with the same polarity and with an appropriate amplification and arrives at terminal 2-2 as a timing pulse.

When this timing pulse is applied to the Nw-monostable circuit and an input is not simultaneously present, the timing pulse is reflected `with same polarity with low reflection loss.

Consequently, the timing pulse shuttles between the Nw-monostable circuit and the reflecting circuit with the fundamental period of 2r.

The input pulses P1 and P1 are regenerated in the same manner and sent out from the terminals 4-4 as output pulses P2, P2 and P2, as shown in III of FIG. 13, with the width W and delayed by 1- from the original pulses.

In this case, it must be noted that when the Nw-monostable circuit operates, it has a transient period to recover the stable state. It is shown in III of FIG. 13 in that the trailing part of the regenerated pulse recovers gradually to a steady state. In accordance with this, the circuit configuration should be made such that the sum of recovery time and output pulse width W is smaller than the fundamental period 2f.

By the configuration shown in FIG. 9, the input pulse train is wave-regenerated and retimed into the output pulse train having Iwidth W and fundamental interval 2r. As shown in FIG. 13, the timing pulse is scarcely transmitted to the output side also in this case. Like the configuration shown in FIG. 2, the configuration shown in FIG. 9 also operates stably as against an input pulse having a crest value greater than the threshold level of the NW- monostable circuit.

FIG. 14 shows another embodiment. It is of such a construction that the Nw-bistable circuit of FIG. 2 is used by being connected in series to the line. L300-L300 are choke coils which have impedance great enough for signals. C301-C310 are coupling condensers or bypass condensers which have impedance small enough for signals. The wave regenerating circuit A consists of an impedance converter which is the emitter grounded circuit of transistor T300 and the aforementioned NW-bistable circuit. By regulating resistances R300, R301 and R302, the proper setting is made so that the input impedance of the impedance converter is equal to the impedance Z0 of the line and that its output impedance is adequately smaller than Z0.

The composite transistor circuit Nw is biased at Point A1 of FIG. 4 with the gradient of the straight line al-al by constant voltage diode D300, resistances R300, R304, and coil L302. The straight line [J1-b1 of FIG. 4 is the A-C load line, but its gradient may also be considered to be if the output impedance of the impedance converter is ignored in this case. That is to say, the NW-bistable circuit of FIG. 14 is under the same conditions as that of FIG. 2 with respect to both D-C and A-C, and has the same function.

The nonlinear active reflecting circuit C is the composite transistor circuit S1. with an S-type negative resistance being connected in series to the line by condensers C307 and C310 and stably biased in its negative resistance region. The composite transistor circuit Sr is a variation made from the composite transistor circuit Sr shown in FIG. 5(a) by replacing PNPT/'T40 and NPNT1-T45 and reversing the polarity of the electric source E49. Its V-I characteristic can be obtained by changing the sign for the V-aXis and I-aXis of FIG. 6. The composite transistor circuit S1. is biased in opposite polarity to the bias of the composite transistor circuit Sr shown in FIG. 2 by constant voltage diode D302; resistances R305, R303; and coil L305. The reflection characteristic and transmission characteristic of the Sr'reflecting circuit at terminals 3-3 are naturally in opposite polarity to those of the S,.reecting circuit shown in FIG. 7, The small amplitude input pulse is reflected with amplification changing polarity, while the circuit has such a saturated reection characteristic that the amplitude of the reflected pulse of the negative large amplitude pulse is saturated at a positive, small constant value.

The function of the pulse regenerating system shown in FIG. 14 which comprises the above-described circuits is as follows: Let r represent the one-way propagation time of the delay line B, and a pulse train having a fundamental interval T equal to 4T is to be regenerated. The following explanation is made with reference t FIG. 15. I is the input wave form observed at terminals 1-1. II is the voltage wave form of the NW-bistable circuit observed between terminals tl-tl. III is the output wave form observed at terminal 4-4. Here, as to the polarity of the terminal voltage of the composite transistor circuit, it is considered positive when potential at t1 is higher than that at t1' as defined in FIG. 3(a). In the construction of FIG. 14, the amplitude of the input pulse must always be greater than the threshold level of the Nw-bistable circuit. If a positive input pulse arrives at time t=r0, the NW-bistable circuit is triggered and switched to a high potential state, generating a positive large amplitude positive voltage step between terminals t, and t. Since terminal t1 is connected to terminal 2 and terminal t1 to terminal 2' via C303, the output impedance of the impedance converter and C302 respectively, the large positive voltage step generated at the 'Nw'bistable circuit is applied to terminals 2-2 as a large negative voltage step due to the circuit configuration and it propagates on the line B. A greater part of its energy is sent out to the next stage through terminals 4-4 without being reliected lby the Srre'iiecting circuit. A part of the energy is reflected by the Srreliecting circuit with a change in polarity and thereby becomes a positive small step, reaching terminals 2-2 at a time interval of 2T after the initial switching, and is applied between terminals tl-tl' in negative polarity to switch the NW-bistable circuit from the high potential state D1 which is shown in FIG. 4 to a low potential state F1 of the same ligure. By this switching action a large negative amplitude voltage step is generated in the NW-bistable circuit and this large negative voltage step is applied to terminals 2-2 as a positive voltage step having an amplitude as large as the preceding large negative voltage step due to the circuit conguration and this positive voltage step cancels the trailing part of the preceding negative voltage step after the time 2T to make a pulse having a duration 2-r. This negative pulse is a regeneration pulse of input pulse P1. Input pulses P1 and P1 are regenerated in the same manner owing to it. A greater part of its energy is transmitted through the Srreflecting circuit, while a part of it has its polarity reversed and is reflected, a small negative step therefore reaches terminals 2*-2 after time 4r passes from the time of initial switching. A timing pulse is produced from this small negative step and continues shuttling, with its amplitude gradually decreasing, until the next input pulse arrives. After 4m (nzintegers) from the initial switching, a negative small step which is the front edge of timing pulse arrives at terminals 2-2 from the delay line B and this is applied in positive polarity between terminals tl-tl and controls the operating time of the NW-'bistable circuit. As shown in FIG. 15, this construction makes the output of negative polarity. In case repeating is to be continued for many times, it is permissible if the repeater systems of the configuration of FIG. 14, and the repeater systems which are given by changing the configuration of FIG. 14 to one in opposite polarity having the function to regenerate negative input pulses into positive output pulses are placed alternately.

The change to opposite polarity may be eifected in the following Way: The impedance converter consisting of transistor T300 may be as it is. The Nw-bistable circuit can have its polarity readily reversed by replacing the PNP transistor and NPN transistor, reversing the polarity of the electric source between terminals t1, t1 and making some change in the bias circuit, just as done to change the Sr-reecting circuit to the S,reliecting circuit. As reecting circuit C, Sr-retlecting circuit may 'be used again just as in the case of FIG. 2.

FIG. l5 shows a wave obtainable when there are no uctuations of input on the time axis and the timing pulse has an ideal steepness. Even where there are input uctuations on the time axis, however, the operation is stable enough as explained with respect to the contiguration shown in FIG. 2, since the rising time of the timing pulse is not zero in actuality.

Just as the construction of FIG. 9` using the NW-monostable circuit was obtained from the construction of FIG. 2 using the NW-bistable circuit by altering the inductance value of coil L103, it is possible to use a construction in which the Nw-monostable circuit is connected in series tcthe line as a variation of the construction of FIG. 14. That construction is shown in FIG. 16. The Wave regenerating circuit A of FIG. 16 is quite the same as the wave regenerating circuit A of FIG. 14 and has an output pulse width W, except that the value of inductance of L40Z is by far smaller than that of L302 and the cornposite transistor circuit is made to operate monostably. The bias condition of the composite transistor circuit Nw and the manner of its monostable operation are the same as those of the Nw-monostable circuit of FIG. 9. Just as in the case of the construction of FIG. 14, the output of the wave regenerating circuit A is of negative polarity also in the case of the construction of FIG. 16, so that the nonlinear active reflecting circuit C must be such that it has a saturated reiiection characteristic as against a negative large amplitude input. This can be realized if a circuit made by converting the Nr-reflecting circuit of the construction of FIG, 9 into opposite polarity is used. The composite transistor circuit Nr' is a variation of the composite transistor circuit N, shown in FIG. 11 made by replacing PNP transistor T35 and NPN transistor T30, reversing the polarity of the electric source E37 and reversing the direction of diode D33. This is biased in opposed polarity to the bias of FIG. 9 by constant voltage diode D401; resistances R405, R400; and coils 1,405, L406. The reflection characteristic and transmission characteristic of the Nrreecting circuit at terminals 3-3' are naturally in opposed polarity to those of the Nr-reiiecting circuit shown in FIG. 12. It reflects a small amplitude pulse with amplification without -changing polarity, and has a saturated reflection characteristic as against a negative large amplitude pulse of saturation at a negative, iixed small level. The operation of the pulse regenerating system of the construction of FIG. 16 is shown in FIG. 17. I of that figure is the input Wave form observed at terminals 1-1, II is the voltage wave form of the Nwrnonostable circuit observed at terminals tl-tl, and III is the output wave form observed at terminals 4-4.

FIG. 17 shows a situation Where the timing has grown in the pulse regenerating system.

When the input pulse P1 and any timing pulse are applied to the Nw-monostable circuit at a time t=r0 simultaneously, the resultant waveform formed by these two pulses exceeds the threshold level of the Nw-monostable circuit at the time t=t0 and triggers the NW-monostable circuit because the timing pulse has a steep rise occurring at time t=t0 and generates a large amplitude positive pulse having a width W as a regeneration pulse of input pulse P1. This regeneration pulse appearing between terminals tl-tl is applied to terminals 2-2 via capacitor C403, the output impedance of the impedance converter and capacitor C402 and via another path by capacitor C400 aS a large negative pulse. This large negative pulse propagates on the line B and arrives at terminals 3-3 of the reflecting circuit having a saturation characteristic and an ampliiication retiection at a time t=r0l1n When the large negative pulse arrives at the Nr-reection circuit, a large part of this pulse exceeding the critical value of the reecting circuit passes through this circuit and another part 15 of the pulse is reflected towards thc Nw-monostable circuit with the same polarity and `with an appropriate amplification and arrives at terminals 2-2 as a timing pulse at a time t=t0|21.

When this timing pulse is applied to the NW-monostable circuit and an input pulse does not exist simultaneously, the timing pulse is reflected with same polarity with low reflection loss.

Consequently, the timing pulse shuttles between the NW-monostable circuit and the reflecting circuit with the fundamental period 2f.

The input pulses P1 and P1 are regenerated in the same manner and sent out from the terminals 4 4 as the output pulses P2, P2 and P2" of negative polarity having the width W and delayed by Fr from the input pulses as shown in III of FIG. 17.

In the instance of the circuit configuration of FIG. 16, it should be taken into account that the sum of recovery time and output pulse width W is smaller than the fundamental period 2T.

In all of the aforementioned embodiments shown in FIG. 2, FIG. 9, FIG. 14 and FIG. 16, a pulse regenerating circuit of negative resistance of N-type is used as the wave regenerating circuit. From the theory of duality, however, it is readily conceivable that a construction using a pulse regenerating circuit of negative resistance of the S-type as a wave regenerating circuit is also possible. Four embodiments are shown in FIG. 18, FIG. 19, FIG. 20 and FIG. 2l, and these are in dual relation to the embodiments shown in FIG. 2, FIG. 9, FIG. 14 and FIG. 16 respectively. The composite transistor circuit SW used in the constructions of FIGS. 18-21 is a circuit of the construction shown in FIG. 22(a) and is represented by the symbol shown in FIG. 22(17). In FIG. 2201), t2, r2' and P2 are terminals, T20 and T20 are transistors, R21, R22 and R23 are resistors, E29 is a constant voltage power source. V shows a voltage applied between terminals t2 and t2', and is defined to take positive value wherein a potential at terminal l2 is higher than that at terminal t2. I shows a current which flows into terminal t2 and flows out from terminal t2. The V-I characteristic between the terminals lf2-z2 of this circuit shows an S-type negative resistance as shown in FIG. 23. In FIG. 23, there are two positive resistance regions which are separated by a negative resistance region. The one at the smaller current side of the negative resistance region is called the first positive resistance region, and the other is called the second positive resistance region.

The various values defining the V-I characteristic curve are as follows:

V22: a voltage of the transition point between the negative resistance region and the first positive resistance region IP2: a current of the transition point between the negative resistance region and the first positive resistance region 172: a current of the transition point between the negative resistance region and the second positive resistance region Ra2-1: a gradient in conductance of the V-I curve in the first positive resistance region RM-1: a gradient in conductance of the V-I curve in the negative resistance region R.,2-1: a gradient in conductance of the V-I curve in the second positive resistance region These values are given in the following formulae using circuit constants shown in FIG. 22(a) Where, V025 is the emitter diffusion potential of transistor T25, V027 is the diffusion potential of diode D27, V227 is the forward resistance of diode D27 and lz is the number of diode D27. A feature of this V-I characteristic is that impedance is very low in the positive resistance region on the small current side of the negative resistance region.

The pulse regenerating operations of the pulse regenerating systems of the configurations shown in FIGS. 18-l are quite the same as those of the configurations using composite transistor circuits NW in dual relation. Here we will explain the operation of the system of FIG. 18 for example in comparison with that of FIG. 2.

The wave regenerating circuit A comprises an impedance converter using transistor T500 in the common emitter configuration and an SW-bistable circuit of the bistably biased composite transistor circuit Sw connected in series to the line. The impedance converter is the same as that in the configurations of FIG. 14 and FIG. 16. Its input impedance is equal to the impedance Z0 of the line, and the output impedance is adequately smaller than Z0. The composite transistor circuit SW is biased at Point A2 in FIG. 22 by a constant voltage diode D500 and resistance R503. The straight line z2-a2 is the D-C load line and its gradient is Rm-1. The value of R503 is adequately larger than Z0, and is consequently considered open for signals. The straight line b2-b2 is the A-C load line and, if the output impedance of the T500-impedance converter is ignored, its gradient is The impedance of the A circuit at terminals 2-2' as viewed from the side of the delay line B, is given a value such that an incident wave reflects with little loss. Generally, it is maintained in an open condition for the N- type negative resistance composite transistor circuit, such as found in the circuits of FIGS. 2, 9, 14 and 16, and in a shortcd condition for the S-type negative resistance circuit now being discussed in connection with FIGS. 18-21.

As defined in FIG. 2201), the current that ows in from terminal t2 and ows out from terminal t2 is considered to be the current in the positive direction. Since Roc2-1gw in FIG. 23, the circuit SW has low impedance as against a small amplitude pulse which does not exceed the threshold level 122-102 in the proximity of Point A2. It a positive input exceeding the threshold level is applied between terminals t2, t2', the circuit SW is triggered and switched to the large current state D2 via Points B2, C2, generating a positive large amplitude current step. Point D2 is not a direct-current-wide stable point, and the operating point of the circuit S.,V gradually shifts from Point D2 to Point E2 in accordance with a very large time constant which is determined mainly by C505, but it can be considered approximately a stable point in relation to such a short time as the repetition interval of the pulse signals.

When a negative input so large that the operating point exceeds Point E2 is applied to the composite transistor circuit Sw located at Point D2, the circuit SW is again triggered and switched to A2 via Points E2, F2, generating a negative large amplitude current step. That is to say, the circuit SW of FIG. 18 operates bistably. The nonlinear active reliecting circuit C is the Nr-reiiecting circuit used in the construction of FIG. 9.

In the construction of FIG. 187 the small amplitude pulse shuttling on the wave delay line B is reflected in reversed polarity with low loss at terminals 2 2 and is reflected with amplification without changing polarity at terminals 3 3. Like the construction of FIG. 2, the con struction of FIG. 18 regenerates a pulse train which has a fundamental interval equal to four times the one way transmission time 1- of the delay line B. In this contiguration, because of the aforementioned terminal conditions, a positive small amplitude step arrives from the delay line B at terminals 2-2 after a half cycle (=2T) passes from the time the Sw-bistable circuit is switched from the small current state A2 to the large current state D2, and a negative small amplitude step after one cycle (=4-r) passes, their polarity being opposite to that shown in FIG. 2. In FIG. 18, however, the terminal t2' of the circuit SW is connected to the terminal 2 by coupling condenser C505, and the terminal t2 to the terminal 2 via coupling condenser C502, T500-impedance converters output impedance and coupling condenser C502, So that the aforementioned small step after the elapse of a half-cycle is applied between terminals t2-l2 as a negative electromotive force and switches the SW-bistable circuit from large current state to small current state, while the aforementioned negative small step after the elapse of one cycle is applied between terminals t2-t2 as positive electromotive force and increases the sensitivity of the SW-bistable circuit, controlling the operating time of the SW-bistable circuit if the next input pulse arrives at that point of time. That is to say, it operates in the same way as the constitution of FIG. 2.

FIG. 8, which shows the operation of the pulse regenerating system of the configuration of FIG. 2, may be considered to show the operation of the pulse regenerating system of FIG. 18 if II of that figure is considered to represent the time waveform of the current which flows from terminal t2 to terminal t2 of the composite transistor circuit SW. This is also applicable to the other three configurations. If the graph II of FIG. 13, FIG. 15, and FIG. 17 is considered to be the time waveform of the current which flows from terminal t2 to terminal t2 of the composite transistor circuit SW, they show the operation of the pulse regenerating systems of the configuration of FIG. 19, FIG. 20, and FIG. 21 respectively. In FIG. and FIG. 21, the composite transistor circuit SW operates as a monostable regenerating circuit. That is to say, C705 of FIG. 20 and C802 of FIG. 21 are sufriciently small as compared with C505 of FIG. 18 and C005 of FIG. 19, so that in FIG. 23 the large current state D2 can no longer be considered to be the approximate stable point and the state of the composite transistor SW after switching to the large current state quickly shifts from Point D2 towards Point E2. C703 and C502 are both so set that the output pulse width of the S50-monostable circuit is W.

For conveniences sake, a composite transistor negative resistance circuit was used in the eight examples of embodiment that have been explained. This invention, however, is not limited to them. ln the present invention, two negative resistance devices are used, one in the wave regenerating circuit and one in the nonlinear active reflecting circuit. The former, biased in the positive resistance region on one side, performs switching operation between it and the positive resistance region on the other hand with a negative resistance region in-between, while the latter, biased in the negative resistance region, operates as a nonlinear resistance element. Consequently, as the active element of the nonlinear active reflecting circuit, a negative resistance device capable of being stably biased in its negative region is desirable. As an N-type negative resistance device, there is the Esaki diode for example and this is capable of stable bias in the negative resistance region and can therefore be employed as the active device of any of the aforementioned circuits. As an S-type negative resistance device, there is the PIN diode for example. As this cannot be biased in a negative region stably, it

can be used only as the operating; device of a wave regenerating circuit. At the present moment no S-type negative resistance device which can be stably biased in its negative region has yet been developed, but, when such a negative resistance device is developed in the future, it is quite natural that it will be possible to use it for the nonlinear reflecting circuit of the present invention.

For conveniences sake, we have explained the present invention with respect to its operation on a unipolar pulse. However, those skilled in the trade can readily understand that pulse regenerating apparatuses for a bipolar pulse and Various other patterns may be made in accordance with the principle of the present invention by making slight modification in the conguration of the circuits.

What we claim is:

1. A pulse regenerating repeater to be installed in cascade in a transmission line to regenerate the amplitude and fundamental period of an attenuated input pulse com-` prising a wave regenerating circuit having a bistate nonlinear negative resistance device for regeneration of a pulse upon the simultaneous subjection thereto of an input pulse and a timing pulse, a timing pulse delay line connected at one end in cascade to the output of said wave regenerating circuit and having a selected time period of propagation to govern said fundamental period for the regenerated pulse, and a reflecting circuit having its input connected in cascade to the other end of said delay line and having a nonlinear negative resistance device which reflects the portion of an incident pulse from said wave regenerating circuit below a preselected value back onto said delay line as said timing pulse and passes the portion above said preselected value for transmission, said wave regenerating circuit having reection means to reflect an incident timing pulse from said delay line in the absence of said simultaneously subjected input pulse to permit the shuttling of said timing pulse back and forth over said delay line.

2. The pulse regenerating repeater of claim 1 characterized by amplification means in said reflecting circuit to amplify said reflected pulse and thereby compensate for the reection loss of the wave regenerating circuit and transmission loss of said delay line.

3. The pulse regenerating repeater of claim 1 characterized in that said bistate nonlinear negative resistance device consists of an N-type (voltage regulated type) negative resistance device connected in parallel to the transmission line and performing bistable operation, and said reflecting circuit nonlinear negative resistance device consists of an S-type (current regulated) negative resistance device connected n parallel to the transmission line.

4. The pulse regenerating repeater of claim 1 characterized in that said bistate nonlinear negative resistance device consists of an N-type negative resistance device connected in parallelfto the transmission line and performing monostable operation to generate a pulse having a width such that the sum of the time of said pulse width and the recovery time of said device is smaller than said fundamental period, and said reflecting circuit nonlinear negative resistance device consists of an N-type negative resistance device connected in series to the transmission line.

5. The pulse regenerating repeater of claim 1 characterized in that said bistate nonlinear negative resistance device consists of an N-type negative resistance device having bistable operation, and said reflecting circuit nonlinear negative resistance device consists of an S-type negative resistance device connected in parallel to the transmission line.

6. The pulse regenerating repeater of claim 1 characterized in that said bistate nonlinear negative resistance device consists of an N-type negative resistance device connected in series to the transmission line and performing monostable operation, and said reilecting circuit nonlinear negative resistance device consists of an N-type 19 negative resistance device connected in series to the transmission line.

7. The pulse regenerating repeater of claim 1 characterized in that said bistate nonlinear negative resistance device consists of an S-type negative resistance device connected in series to the transmission line and performing' bistable operation, and said reecting circuit nonlinear negative resistance device consists of an N-type negative resistance device connected in series to the transmiyssion line.

S. The pulse regenerating repeater of claim 1 characterifed in that said bistate nonlinear negative resistance device consists of an S-type negative resistance device connected in series to the transmission line and performing monostable operation, and said reecting circuit nonlinear negative resistance device consists of an S-type negative resistance device connected in parallel to the transmission line.

9`. The pulse regenerating repeater of claim 1 characterized in that said bistate nonlinear negative resistance device consists of an S-type negative resistance device connected in parallel to the transmission line and performing bistable operation, and said reilecting circuit nonlinear negative resistance device consists of an N-type negative lresistance device connected in series to the transmission line.

1Q. The pulse regenerating repeater of claim 1 characterized in that said bistate nonlinear negative resistance device consists of an S-ty'pe negative resistance device connected in parallel to the transmission line and performing monostable operation, and said reflecting circuit nonlinear negative resistance device consists of an S-type negative resistance device connected in parallel to the transmission line.

11. The pulse regenerating repeater of claim 1 wherein said deiay line consists of a portion of transmission line.

12. The pulse regenerating repeater of claim 1 characterized by electric power supply means connected to said transmission line for the operation of said repeater by electric power supplied via said transmission line.

References Cited UNITED STATES PATENTS 2,585,571 2/1952 Mohr 325-13X 2,878,325 3/1959 Merrill, Jr. 179--170 3,124,648 3/1964 Miller 178-70 3,141,138 7/1964 Oshima et al. 179-170X 2,502,942 4/1950 Goodall 179--15X 2,868,965 1/1959 DeLange 179-15X 2,912,583 11/1959 Geyer, .Ir 328--164 3,028,489 4/1962 Chasek 179-15X 3,085,200 4/1963 Goodall 179-155( 3,176,076 3/1965 Hyman 325-13X ROBERT L. GRIFFIN, Primary Examiner A. H. I-IANDAL, Assistant Examiner 

